Quad-tile Intel Xe-HP GPU

At last week’s Intel Architecture Day, Intel Chief Architect Raja Koduri briefly introduced the smaller member of the company’s upcoming Xe-HP series of server processors, the configuration to a tile. Now, just days later, he’s raised the bar by showing off the larger four-tile setup.

Designed to be a scalable chip architecture, Xe-HP is expected to be available with one, two or four tiles. And while Intel has yet to divulge too many architectural details, based on their packaging disclosures, it looks like the company is using its EMIB technology to wire GPU tiles, as well as the onboard HBM memory. to the GPU. .

Assuming it’s released, a multi-tile GPU – essentially multiple GPUs in a single package – would be a major achievement for Intel. GPUs are notoriously bandwidth-hungry due to the need to split data across cores, caches, and command interfaces, making them non-trivial to chiplet / mosaic split. Even though Intel can only use this type of multi-tile scalability for compute workloads, it would have a significant impact on the type of performance that a single GPU package can achieve and how future servers might. be built.