AMD Unveils Era Of Multi-Layer Chip Design Starting With Zen 3 With 3D Stacked V-Cache Technology

AMD has further detailed its future multi-layer chip design technologies that will be integrated into next-generation processors such as the upcoming Zen 3 chips with 3D V-Cache technology.

AMD Talks Next Generation Multilayer Chip Designs Featuring 2D / 2.5D and 3D Hybrid Chip Technologies

The company talked about its existing chip designs and what the future holds in terms of multi-layered chip progression at HotChips 33. Currently, there are 14 chip package architectures in development for various products that have already been released or released. coming out very soon. AMD states that the choice of packaging and chip architecture depend on the performance, power, area and cost of the respective product (PPAC for short).

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According to AMD, 2021 will mark the first introduction of its Chiplet 3D architecture design. We’ve seen 2D and 2.5D packaging on consumer and server products before, but with 3D V-Cache, we’re finally going to get into 3D chip stacking. The first product to incorporate this technology will be AMD’s Zen 3 core, which will feature an SRAM cache on the main Zen 3 CCD. The use of 3D chiplet technology also increases the interconnect density while staying in the weakest power and area. Some figures for the 3D V-Cache technology present on Zen 3 CCD are listed here.

AMD explained how it integrates 3D V-Cache on top of its Zen 3 CCD. This is achieved through the use of Micro Bump (3D) and multiple TSV interconnects as mentioned above. The interconnect uses a brand new hydrophilic dielectric-dielectric bond with CU-CU direct bond that was designed and co-optimized in close partnership with TSMC. The two individual silicones (chiplets) are bonded together using this technology.

According to AMD, the hybrid link has a 9u pitch and a TSV-like backend which is slightly smaller than Intel’s Forveros interconnect which has a 10u pitch. The energy efficiency of the interconnect is rated over 3 times compared to Micron Bump 3D, the interconnect density is rated over 15 times that of Micron Bump 3D and these 3D chips also offer better signal / power thanks to the lowering of the TSV capacitance, inductance.

AMD also points out that on-CPU DRAM is just the start of what they could achieve with 3D stacking. Going forward, AMD expects to leverage 3D stacking to stack cores on cores, IP on IP, and things get really crazy when macroblocks could be stacked in 3D on top of it. other macro blocks.