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How do we know it? AMD did not give specific details about Rome, at least not at the level of fine grains. However, with an imminent launch and silicon already in circulation, leaks are inevitable.
This brings us to a database entry for SiSoft Sandra, a popular evaluation and diagnostic utility that we use ourselves in some of our journals. For a brief period, there was an entrance for a 2P AMD Rome Epyc machine. Unfortunately, the entrance seems to have been removed, but fortunately not before TechPowerUp could take a screenshot.
Click to enlarge (Source: TechPowerUp via SiSoft Sandra)
The database entry shows a system with a pair of Epyc Rome processors at 64 cores, each consisting of eight chiplets of Zen processors 2 at 8 nm of 7 nm paired with a controller chip of E / S of 14 nm, as previously reported by AMD. The controller chip manages PCIe memory and connectivity tasks.
As there are eight chiplets, this seems to indicate that each of them has 16 MB of L3 cache, the 8 cores of the chip being divided into quad-core CCX units each containing 16 MB of L3 cache. If true, L3 cache doubles by CCX, which can facilitate data transfers between chiplet and I / O.
This assumes that everything is read and extrapolated correctly. Keep in mind that this data comes from a third party utility and that both Rome chips are technical examples, which means that they may not indicate the final hardware. However, there are usually no major changes at the end of the game.
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