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Today, at the Next Horizon event, AMD unveiled substantial new details about its 7nm processor, christened Rome. The new chip debuts at an important time for AMD. Its first processor CPU, Epyc, was welcomed and adopted, including a new announcement of support by Amazon. Epyc 2 is, in some ways, even more important. Businesses are inherently conservative and companies do not tend to switch from one processor provider to another immediately. Integrating AMD processors into more businesses means demonstrating a sustainable roadmap and the ability to deliver new generations of products that continue to be competitive. AMD's revelations in Rome imply that their first 7-nm chip will actually deliver these gains. (Apologies for the potato photos – I am a recognized miserable photographer.)
According to Mark Papermaster, AMD's CTO, second-generation Epyc processors will deliver significant improvements over their original design. Floating point throughput has been doubled with the adoption of 256-bit AVX2 registers. Load / storage bandwidth was also doubled, and the bandwidth distributed and removed from the processor increased, as did the micro-op cache. EPYC
These enhancements should collectively significantly improve the performance of Epyc and Ryzen, although AMD has not specified whether it would reduce the clock speed of the Ryzen and Epyc processors to 7 nm if it was running AVX2 in the same way as Intel. 128-bit AVX2 support worked pretty well for AMD at Ryzen – tests and comparisons of servers showed that while Intel had a definite advantage over some FPU workloads, AMD was quite powerful, even superior in terms of performance.
For PCIe 4.0 support, AMD will offer backward compatibility with existing Naples platforms and future compatibility with the AMD Milan platform, warranty. This means that the processor can use PCIe 3.0 or 4.0 depending on the platform in question.
Infinity Fabric is also undergoing a major upgrade, although some details have not been revealed. As some have predicted, Epyc 2 will be AMD's first processor to deploy chiplets based on 7 nm while the I / O block is built on 14 nm. It's not necessarily a bad thing. As node narrowing progressed, contact and interconnect resistance became a major limiting factor for improving overall performance. There are not necessarily many intrinsic benefits to simply packing more threads and pellets into smaller and smaller spaces. AMD therefore divides its I / O and connectors into two separate sections.
The current implementation of AMD's Infinity Fabric is wired as below (focus on the clearer arrows of each processor, not cross-links between processors).
The new second-generation Infinity Fabric is quite different:
The impact this will have on latency is unclear, but it shows how AMD will avoid what might have been a significant problem. With eight DDR4 channels and probably doubled chip density (AMD alluded to it without giving any formal count for Epyc 2), AMD would have only one DDR4 channel per eight processor cores. This is significantly lower than previous models. This approach should avoid this problem by making all DDR4 bandwidth available for all core sets needed to access it.
We still do not have specific details, such as improving the power consumption of Infinity Fabric or the bandwidth provided by the new processors. I would warn readers not to conclude that these load / storage rate and FPU enhancements will have a significant impact on performance. The degree of uplift will depend on the specificities of the application and the locations of the bottlenecks in the original design of the Epyc. If you remember, Haswell had promised a number of substantial bandwidth and low bandwidth gains, but the actual increase in most software was much smaller.
Nevertheless, Epyc 2 looks like a powerful chip based on what we have seen so far. We do not know the exact clocks nor the distribution of the cores, beyond a maximum 64-core processor (an internship comment seemed to imply that setting the clock on 7 nm is small, but we have not yet could confirm it). But between the gains in CPI and the expected increase in the number of cores, Epyc 2 should generate a significant increase over its predecessor.
According to Lisa Su, Rome will offer 2x per socket performance improvement and 4x socket FPU performance over previous generation processors. This is a huge improvement claimed and we expect it to fit the best of scenarios – applications that do not scale perfectly from 32 to 64 cores will not achieve this goal – but under the right circumstances, Epyc 2 should be a performing titan.
The only warning to that? AMD gave no indication as to when the processor could start, beyond "2019." # 1H, # 2H. This latest information, provided at the end of the presentation, makes it much harder to assess the potential impact of the launch. If 1H is generally interpreted to mean "June", "2019" can also be interpreted to mean "December" according to exactly the same theory. It seems unlikely that this is true, but the lack of a schedule, even quarterly, has undermined the energy generated by AMD's announcement.
Now read: Nvidia Tesla and AMD Epyc Power New Berkeley Supercomputer, Epyc: AMD Now Available for Oracle Cloud Compute Instances, and AMD Will Produce its 7nm Epyc "Rome" Processors at TSMC, Not GlobalFoundries
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